started by [Theo Verelst] Modern computers (except very rare quantum and analog ones) all work on the basis of binary logic, so lets see if with modern tachnology we can program some decent logical circuits in this case with the help of tcl and [bwise]. Consider this 'flow graph' or schematic: newproc {set and.o [expr ${and.i1} & ${and.i2}]} and {i1 i2} o 40 {} {} 290 110 newentry 60 30 {} {} 72 108 newmon 0 80 65 {} {} 410 110 newproc {set bits.o2 [expr (${bits.i} & 2) >> 1] ; set bits.o1 [expr ${bits.i} & 1]} bits i {o1 o2} 40 {} {} 188 108 connect wire0 Entry1 out bits i connect wire1 and o Mon1 in connect wire2 and i1 bits o1 connect wire3 and i2 bits o2 which when loaded (or sourced in the console) in [bwise] looks like: [http://82.171.148.176/Wiki/logic4.gif] The point is that we fill in a bit pattern (as number between 0 and 3, 2 bits), take the and function of the two bits in that number, and show the result as 0 or 1 (in this case). Now we want to make a Xilinx FPGA (Field Programmable Gate Array) which can be bought cheap enough to do our and function for us in 'hardware'. Such a chip is programmed to perform a certain set of logical functions at startup by reading in a pattern from ( a megabit of) flash memory, and then acts as the programmed circuit, in this case of fair complexity (a whole microcontroller can be programmed in using less than 10% of the chips resources), but we make a simple circuit: one '''and gate'''! To get this gate of ours to work in the xilinx programmable logic chip, I prefer to also program in a (much more complicated) serial port interface, so we can use a little tcl script to talk with our AND gate over a standard serial connection at 100 kbp/s using binary data. This is the schematic diagram of the setup, which at the same time is the top level of the circuit we program in the xilinx devenv's schematic entry program: [http://82.171.148.176/Wiki/logic1.gif] The logic block is where our and gate goes, the upper block is a compound consisting of a few levels of hierarcy of hardware description (in vhdl) which defines the serial interface, the 'out' is fed to the and gate, and the 'in' is read back 1/(50e6) sec (20 nano seconds) or so later. So we can send a byte over the serial port, the and gives its result, which is immedeately read and send back to the serial port. To make the xilinx act like an and function we program a block to that extend in [VHDL], which can later be automated with tcl and bwise: [http://82.171.148.176/Wiki/logic2.gif] after this the whole circuit has been 'compiled' into a xilinx programming file using the IDE (called ISE webpack), by making a project for the right chip (in this case a xc3s2000-4ft256), importing the serial source files, creating schematic symbols from the 'serial' and 'logicblock' files, and updating and saving the symbols in the serial and top schematics, and then selecting top.sch and double clicking generate programming file. The programmer is started by double clicking 'Configure Device' , when the parallel port cable is connected with the special cable from the Digilent/Xilinx Spartan-3 starter board kit (see [http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3-CPLD-DK] for web purchace, $99) to the jtag pins, it can search out for itself what chips are connected, in this case the fpga and a serial flash. I use direct programming in this case, so the fpga gets the top.bit file configured to it, and the flash is set to 'bypass' in the programmer. then 'program' will load the above in the xilinx chip, and the board can be connected up to the serial port. [http://82.171.148.176/Wiki/xilledson.jpg] To communicate with the result, this tcl script is used: set fh [open COM1: RDWR] fconfigure $fh -blocking 0 -mode 115200,n,8,1 -translation binary -buffering full fileevent $fh readable { set w [read $fh] ; foreach c [split $w {}] {binary scan $c H* a; set v $a} } proc w h { global fh puts -nonewline $fh [binary format H* $h] ; flush $fh } fileevent stdin readable { w [gets stdin]; } while {1} { vwait v flush $fh puts -nonewline $v flush stdout } It waits for one byte in hex to be given over the keyboard (followed by ) which it sends to to serial port, and then waits for a byte to get back, which is then printed on the next line in hex, while the program waits for the next input. Input-ing all possibilities from 00 to 11 gives: [http://82.171.148.176/Wiki/logic3.gif] Which is correct because the output is only 1 (high) for the input combination 11(bin) which is 3(hex). We can also change the VHDL code above to make an or gate instead of a nand: o <= "0000000" & (i(1) or i(0)); then the result (after 'recompiling' the circuit and loading it in the chip) becomes: 00 0001 0102 0103 0100 00 which is correct too: the or is only 0 for 00 at its inputs. ---- [TV] (Nov 20 2005) I've installed Fedora core 4 Linux in 64 bit version on a athlon64 (3300) upgraded PC, and wondered what to do about (currently) the lack of windows (the old XP gives a blue screen in seconds...) to drive the parallel port programmer cable, and found out there is a good tool to replace IMPACT to do the actual programming of the xilinx '''or''' the flash memory, which is called ''xc3sprog'' [http://www.rogerstech.force9.co.uk/xc3sprog/] which when compiled (also on 64 bit OS) nicely works by using: ./xc3sprog top.bit And on Linux the serial script (run from a terminal, in my case a remote X terminal) probably should become (in my case): set fh [open /dev/ttyS0 RDWR] fconfigure $fh -blocking 0 -mode 115200,n,8,1 -translation binary -buffering full fileevent $fh readable { set w [read $fh] ; foreach c [split $w {}] {binary scan $c H* a; set v $a} } proc w h { global fh puts -nonewline $fh [binary format H* $h] ; flush $fh } fileevent stdin readable { w [gets stdin]; } while {1} { vwait v flush $fh puts -nonewline $v flush stdout } or whatever your linux serial port is called... This was hacked quick, so maybe someof you can say how the above script would work with redirection of the stdin from a file (in the shell that is). See also [Bwise deCasteljau algorithm example] for a hardware implementation of a bwise schematic (''not'' automatic...) centered around a this subdivision algorithm: [http://82.171.148.176/Wiki/xbez2.jpg] It has a handy, generally usable serial interface and 4 byte demx/mux (every bytes get send to and read from a seperate interface), which here drives this algorithms implementation: [http://82.171.148.176/Wiki/xbez1.jpg] The whole project for ISE can be downloaded here: [http://82.171.148.176/Wiki/Bezier.zip] The tcl script can be used to input data and get (hex) data back, which cycles very four bytes, and shows the output of the subdivision, which works correct (after short test). ---- (more to follow on bwise simulation link and circuit generation) ---- I'm working on driving another much bigger FPGA project which is a sound synthesizer which is programmed over a serial link, see here: http://www.theover.org/Fpgasynth , this is NOT a design by yt, but it shoud be interesting to make a Tk interface for it. I made a test slider, which of course is easy in Tk: scale .sl -from 16384 -to 0 -tickinterval 1000 pack .sl -expand y -fill y I made a serial link with the board on COM5 using 9600 kbps, and I made a test to send it a simple note on / note off message: # open the serial port acting as MIDI set fh [open COM5: RDWR] fconfigure $fh -blocking 0 -mode 9600,n,8,1 -translation binary -buffering full #A procedure to send HEX codes to the board: proc w h { global fh ; foreach c [split $h] { puts -nonewline $fh [binary format H* $c] } ; flush $fh } # Testing with a middle C note on and noteoff (this project appears to use velocity==0 instead of noteoff message) w { 90 3C 40 } after 1000 {w { 90 3C 00 }} [http://82.171.148.176/Fpgasynth/01072008318bm.jpg] ---- !!!!!! %| [Category Device Control] | [Category BWise] |% !!!!!!