started by [Theo Verelst]

Modern computers (except very rare quantum and analog ones) all work on the basis of binary logic, so lets see if with modern tachnology we can program some decent logical circuits in this case with the help of tcl and [bwise].

Consider this 'flow graph' or schematic:

 newproc {set and.o [expr ${and.i1} & ${and.i2}]} and {i1 i2} o 40 {} {} 290 110
 newentry 60 30 {} {} 72 108
 newmon 0 80 65 {} {} 410 110
 newproc {set bits.o2 [expr (${bits.i} & 2) >> 1] ; set bits.o1 [expr ${bits.i} & 1]} bits i {o1 o2} 40 {} {} 188 108
 connect wire0 Entry1 out bits i 
 connect wire1 and o Mon1 in 
 connect wire2 and i1 bits o1 
 connect wire3 and i2 bits o2 

which when loaded (or sourced in the console) in [bwise] looks like:

[http://82.170.247.158/Wiki/logic4.gif]

The point is that we fill in a bit pattern (as number between 0 and 3, 2 bits), take the and function of the two bits in that number, and show the result as 0 or 1 (in this case).

Now we want to make a Xilinx FPGA (Field Programmable Gate Array) which can be bought cheap enough to do our and function for us in 'hardware'. Such a chip is programmed to perform a certain set of logical functions at startup by reading in a pattern from ( a megabit of) flash memory, and then acts as the programmed circuit, in this case of fair complexity (a whole microcontroller can be programmed in using less than 10% of the chips resources), but we make a simple circuit: one ''and gate''!

[http://82.170.247.158/Wiki/logic1.gif]

[http://82.170.247.158/Wiki/logic2.gif]

[http://82.170.247.158/Wiki/xilledson.jpg]


 set fh [open COM1: RDWR]
 fconfigure $fh -blocking 0 -mode 115200,n,8,1 -translation binary -buffering full
 fileevent $fh readable {
    set w [read $fh] ;
    foreach c [split $w {}] {binary scan $c H* a; set v $a}
 }
 proc w h {
    global fh
    puts -nonewline $fh [binary format H* $h] ; flush $fh
 }
 
 fileevent stdin readable { w [gets  stdin]; }
 while {1} {
    vwait v
    flush $fh
    puts -nonewline $v
    flush stdout
 }


[http://82.170.247.158/Wiki/logic3.gif]

  o <= "0000000" & (i(1) or i(0));

 00
 0001
 0102
 0103
 0100
 00