Version 0 of Clock divider BWise example

First my interests from the page about Network Theoretical Elements in Bwise and second the general interest raised about fundamental computer science (which I cannot help but see in the circuits, not the software) led to this examples of having something (a socket, a proc, a bwise block, a generator, a clock pulse) which generates a clock signal, which is a paced, repeated change, which feeds i this case 3 divider blocks to generate derived rates.

The generator in the example could be a high frequerncy generator, which is devided a few hundred times in the dvi1..3 blocks to generate square waves (most likely) which form a minor triad chord at their combined outputs.

enter categories here