by [TV]

Using [Bwise] we´d like to be able to play with a Field Programmable Logic Array, preferably one with not negligable computations power and readily available and not too expensive, and in this case using a modest ethernet connection. The idea is to get data from bwise block inputs to the fpga, and let some processing take place with that data, and get results back from the FPGA over the ethernet which is put on the outputs of the bwise block. In principle when a connection is possible any dataformat and any number of distinct bwise-fpga blocks would be possible, but I use the ethernetboard example code to get 10 registers input and 10 registers output which correspond with 10 inputs and outputs on a bwise block, taking hex and writing decimal data per pin representing 8 bit numbers.

As an extension of the idea in [Bwise, a serial port tcl script and a Xilinx demo board] I used:

 * Spartan 3 board [http://www.xilinx.com/products/devkits/HW-SPAR3-SK-UNI-G.htm]
 * Digilent Ethernet module [http://digilentinc.com/Products/Detail.cfm?Prod=NET1&Nav1=Products&Nav2=Accessory]
 * Digilent Adept suite [http://www.digilentinc.com/Software/Adept.cfm?Nav1=Software&Nav2=Adept]
 * the Cygwin compiler on windows XP [www.cygwin.com], though I guess Ming will work, too.

To create a block with 10 inputs and outputs on the bwise canvas (drag to put in place) use the console to type (or cut and paste):

 newproc {} FPGA {i1 i2 i3 i4 i5 i6 i7 i8 i9 i10} {o1 o2 o3 o4 o5 o6 o7 o8 o9 o10}

The function to communicate the pins with Tcl variables associated with them to and fro the fpga using the program from below:

 proc fpgablock {} {
   set in {} ; 
   for {set i 1} {$i <= 10} {incr i} {append in "[uplevel #0 set FPGA.i$i] "}
   set r [exec ./relay.exe << $in]
   for {set i 1} {$i <= 10} {incr i} {uplevel #0 set FPGA.o$i [lindex $r [expr $i-1]]}
 }

And link this argumentless function with the the block (of course there are other ways to make this all work, too):

 set FPGA.bfunc fpgablock

Now we have the block:

[Image Bwise fpgablock1.gif]

Use rightclick on the block and 'info' to get:

[Image Bwise fpgainfo1.gif]

The needed communication program can be built from this souce [http://www.theover.org/Bwise/relay.cpp]

and be compiled with cygwin on windows XP (Pro in this case) because I don´t know a Linux Adapt software version like this:

 gcc -mno-cygwin -o relay.exe -I ../Adept\ sdk\ files/ -L ../Adept\ sdk\ files/ relay.cpp -ldpcutil

test with
 echo '00 00 00 00 00 00 00 00 00 00' | ./relay
gives back the 10 register contents, after the 10 writable regs have been set according to the hex data fed to stdin, when you have made the ethernet board the default Adapt board with the install tool.

Speed: sub second easily but probably not very many invokations per second. (Connected over a giga ether switch network, actually at a Gb/s for the notebook driving the ethercard, which however is connected at 10(!)Mb/s, so fairly slow.)

Current vhdl/schematic to fill the FPGA with is simply the example coming with the ethernet board, possibly with some small modifications (like I made a schematic symbol of the interface, for use (on the same notebook) with Xilinx ISE Webpack 8.2i) The possible speed of the interface is up to over 200 Kilo byte per second tested. The same ethernet connection, which for demonstration purposes can also be connected directly over a single ethernet cable, is used to program the fpga with the required bit file, which is reliable and fast (about a second).


After the above has been installed/compiled/started up, the normally working Bwise block running on some not very old Tcl/Tk version with the executable to drive the hardware in the current directory effectively communicates its inputs when 'eval'-ed or 'fire'-ed as a blcok to the FPGA interface logic, which then can be connected to any fpga processing, and the result is fed back over the ethernet to become visible as the output of the FPGA bwise block, and can be used as (unsigned byte) decimal data in the bwise canvas, or as shown above seen in the info window associated with the block, and interactively used.


See also [List computations in a FPGA, driven by Tcl]

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