http://en.wikipedia.org/wiki/Transputer A transputer is an device/emulator that runs Communicating Sequental Proccesses. Also the basis for the Transterpreter system[http://www.transterpreter.org/wiki/Main_Page] written in pure ANSI C. ---- (dreging info from http://svn.transterpreter.org/transterpreter/trunk/interpreter/dispatch_ins.c) stack based system instruction set is bytecode based with the distinction that first nybble is the main opcode and the second nybble is appended to an (unspecified long) operand register and the contents of that register is then taken as immideate operand. opcode: memnomic: description 0x0 j Jump — add immediate operand to instruction pointer. 0x1 ldlp Load Local Pointer — load a Workspace-relative pointer onto the top of the register stack 0x2 pfix Prefix — general way to increase lower nibble of following primary instruction 0x3 ldnl Load non-local — load a value offset from address at top of stack 0x4 ldc Load constant — load constant operand onto the top of the register stack 0x5 ldnlp Load Non-local pointer — Load address, offset from top of stack 0x6 nfix Negative prefix — general way to negate (and possibly increase) lower nibble 0x7 ldl Load Local — load value offset from Workspace 0x8 adc Add Constant — add constant operand to top of register stack 0x9 call Subroutine call — push instruction pointer and jump 0xA cj Conditional jump — depending on value at top of register stack 0xB ajw Adjust workspace — add operand to workspace pointer 0xC eqc Equals constant — test if top of register stack equals constant operand 0xD stl Store local - store at constant offset from workspace 0xE stnl Store non-local - store at address offset from top of stack 0xF opr Operate - general way to extend instruction set the opr instruction extends the instruction set by switching on the value of the operand register. the extended instruction set is as follows: 0x00 rev 0x01 lb 0x02 bsub 0x03 endp 0x04 diff 0x05 add 0x06 gcall 0x07 in 0x08 prod 0x09 gt 0x0A wsub 0x0B out 0x0C sub 0x0D startp 0x0E outbyte 0x0F outword 0x10 seterr 0x11 mreleasep __PI_SUPPORT__ 0x13 csub0 0x14 extvrfy __PI_SUPPORT__ 0x15 stopp 0x16 ladd 0x19 norm 0x1A ldiv 0x1B ldpi 0x1D xdble 0x1F rem 0x20 ret 0x21 lend 0x22 ldtimer 0x23 boolinvert 0x24 widenshort 0x25 fficall 0x26 lend3 0x27 lendbw 0x28 reschedule 0x2B tin 0x2C div 0x2E dist 0x2F disc 0x30 diss 0x31 lmul 0x32 not 0x33 xor 0x35 lshr 0x36 lshl 0x37 lsum 0x38 lsub 0x39 runp 0x3B sb 0x3C gajw 0x3E saveh 0x40 shr 0x41 shl 0x42 mint 0x43 alt 0x44 altwt 0x45 altend 0x46 and 0x47 enbt 0x48 enbc 0x49 enbs 0x4A move 0x4B or 0x4C csngl 0x4D ccnt1 0x4E talt 0x4F ldiff 0x51 taltwt 0x52 sum 0x53 mul 0x55 stoperr 0x56 cword 0x5A _dup __FPU_SUPPORT__ 0x60 extin __PI_SUPPORT__ 0x61 extout __PI_SUPPORT__ 0x62 minn __PI_SUPPORT__ 0x63 unpacksn __FPU_SUPPORT__ 0x64 moutn __PI_SUPPORT__ 0x65 xminn __PI_SUPPORT__ 0x6C postnormsn __FPU_SUPPORT__ 0x6D roundsn __FPU_SUPPORT__ 0x71 ldinf __FPU_SUPPORT__ 0x72 fmul 0x79 pop 0x7A seminit __PI_SUPPORT__ 0x7B semclaim __PI_SUPPORT__ 0x7C semrelease __PI_SUPPORT__ #ifdef __FPU_SUPPORT__ case \: ins_wsubdb(); break; #endif #ifdef __FPU_SUPPORT__ //in case of fpu support include the below 0x82 fpldnldbi 0x83 fpchkerr 0x84 fpstnldb 0x86 fpldnlsni 0x87 fpadd 0x88 fpstnlsn 0x89 fpsub 0x8A fpldnldb case 0x8B: ins_fpmul(); break; case 0x8C: ins_fpdiv(); break; case 0x8E: ins_fpldnlsn(); break; case 0x91: ins_fpnan (); break; case 0x92: ins_fpordered (); break; case 0x93: ins_fpnotfinite (); break; case 0x94: ins_fpgt (); break; case 0x95: ins_fpeq (); break; case 0x96: ins_fpi32tor32(); break; case 0x98: ins_fpi32tor64 (); break; case 0x9A: ins_fpb32tor64(); break; case 0x9D: ins_fprtoi32(); break; case 0x9E: ins_fpstnli32(); break; case 0x9F: ins_fpldzerosn(); break; case 0xA0: ins_fpldzerodb(); break; case 0xA1: ins_fpint(); break; #endif #ifdef __PI_SUPPORT__ case 0xA2: ins_getpri(); break; #endif #ifdef __FPU_SUPPORT__ //in case of fpu support include the below case 0xA3: ins_fpdup(); break; case 0xA4: ins_fprev(); break; case 0xA6: ins_fpldnladddb(); break; case 0xA8: ins_fpldnlmuldb(); break; case 0xAA: ins_fpldnladdsn(); break; case 0xAC: ins_fpldnlmulsn(); break; #endif case 0xAD: ins_savecreg(); break; case 0xAE: ins_restorecreg(); break; case 0xB0: ins_barinit(); break; case 0xB1: ins_barsync(); break; case 0xB2: ins_barresign(); break; case 0xB3: ins_barenroll(); break; #ifdef __FPU_SUPPORT__ //in case of fpu support include the below case 0xCF: ins_fprem(); break; case 0xD0: ins_i64toreal(); break; case 0xD1: ins_fpdivby2(); break; case 0xD2: ins_fpmulby2(); break; case 0xD3: ins_fpsqrt(); break; case 0xD6: ins_fprz(); break; case 0xD7: ins_fpr32to64(); break; case 0xD8: ins_fpr64to32(); break; case 0xD9: ins_fpexpdec32(); break; case 0xDB: ins_fpabs(); break; case 0xDF: ins_fpchki64(); break; #endif #ifdef __PI_SUPPORT__ case 0xE0: ins_mnew(); break; case 0xE1: ins_mfree(); break; case 0xE2: ins_malloc(); break; case 0xE3: ins_mrelease(); break; case 0xE4: ins_min(); break; case 0xE5: ins_mout(); break; case 0xE6: ins_min64(); break; case 0xE7: ins_mout64(); break; case 0xE8: ins_xable(); break; case 0xE9: ins_xin(); break; case 0xEA: ins_xmin(); break; case 0xEB: ins_xmin64(); break; case 0xEC: ins_xend(); break; case 0xFD: ins_null(); break; #endif ---- [Zarutian] 23. maí 2007: this page is still under construction [Zarutian] 30. maí 2007: and yet I continue ---- [Category Concurrency] | [Category Parallelism]