A part of Concurrency concepts.

- Modern Concurrency Abstractions for C# , Nick Benton , Luca Cardelli , Cédric Fournet , 204
- Polyphonic C♯ is an extension of the C♯ language with new asynchronous concurrency constructs, based on the join calculus. We describe the design and implementation of the language and give examples of its use in addressing a range of concurrent programming problems.

- An implementation model of rendezvous communication , Luca Cardelli , Seminars on Concurrency , 1985

TV: Hmm a pdf from Microsoft research. One of my university fellow students, which *was* toplevel at the time went to the city of grunge for such purpose in name, or to make money. The musical stuff dragged in the terminology doesn't try to hide certain connections, and doesn't conceal an almost complete lack of essential content in the paper it seems. Hoare (csp) is mentioned, that's allways useful, but don't forget that such principles are well implemented in part in the wonderful enough, and non-crashing, UNIX operating system, and some others, too. I mean they meant no shit in the seventies. The theoretical basis is not to impress the paper counters, but to back up why you built something a certain way, such as that one has mathematical reasoning and proof methods to apply to the work one does. Real ones, not politically inspired ones.

TV 2003-07-10: Seeing the page for some reason on the recent page, I thought I'd throw in another 10 C|, or lets see, 25 C| ! The digital circuit design 'theory' or lets say good design practice, tested in practice already in the time of the pdp's and ibms and all that, would make a major distinction between synchronous and asynchronous designs.

By and large synchonous designs are such that there is a single clock (1 0 1 0 1 0 ...) signal which lets operations take place at one of its 'edges' (a 1 --> 0 or a 0 --> 1 transition). The whole circuit obeys this rule, and all that is considered is the state just before the new clock pulse transition, which then determines the 'clocked' signals next state.

A simple gate can be considered an asynchronous circuit, it simply follows its input combinations and computes the corresponding output value as the result of its logical function with a little delay, which is known in the sense of upper bound given certain supply and environment parameters, for instance 20 nanoseconds max, 10 average.

Combinations of gates can make complicated functions, where data ripples through and for which the output is valis when each longest path from the latest input value change has had sufficient time to stabilize the corresponding output values.

When we take such a asynchronous function, we know that if we keep the inputs stable for a certain period of time, the outputs have stably formed the right outcome, assuming the function is designed right.

We could take clocked registers, which are memory cells which memorize the data at its inputs at a certain clock change moment, and put them around asynchronously acting logic, so that the whole circuit can be applied synchronously, or 'clocked'.

Also, there are non-edge but level gated registers, which act synchronously for the one clock edge (falling or rising) when the transition takes place from passing its input to remembering it, and asynchronously while its (asynchronous, I think that was Texas Instruments terminology, commonly shared) clock is set to make the register pass its inputs to its outputs.

Just like on the page I did on memory cells, one can take asynchronous logical functions, and surround them by two non-edge gated registers, and clock them alternatively, which makes the whole circuit synchronous.

The playing with the effective overall delay time (which is not always easy with synchronous circutis) and the right alternating of operating gates is the interesting part of chosing between synchronous and asynchorous logical circuit parts during design.