risc-v assembler

A risc-v assembler/disassembler/emulator in Tcl : code on github

This project now encompasses a simple RISC-V assembler that supports rv32Gc and rv64Gc, a disassembler for the same that will load ELF and an execution emulator that can load ELF and execute the rv32/64 IM tests in the riscv-tests repo. The output of the assembler is still a primitive listing with source line, address and bytes in hex. The disassembler and execution can now load the assembler listing output and statically linked ELF files. It still does not support writing ELF.

Floating point support has been started, but development is stalled. Using Tcl's floats to emulate floating point at the bit compatibility level required to pass the test suite is a bit complex.


Instruction sets and extensions:

  • rv32G (IMAFD_Zicsr_Zifencei)
  • rv64G (IMAFD_Zicsr_Zifencei)
  • C - Compressed instructions
  • E - 16 registers
  • Q - Quad floats
  • Zfinx - Floats in X registers

A very simple example.rva is included. Try make example

    $ make example
    ./rva.tcl -march rv32gc example.rva
     00005 0100 00C58533   add a0 a1 a2
     00006 0104 FFFFC297   auipc t0 top
     00006 0108 12E1       addi t0 t0 top
     00007 010A 8282       jalr x0 t0 0

The accepted instruction sets are defined in files sourced from the opcodes directory. These files derive from those available in the riscv/riscv-opcodes repository, but are highly edited. Additional opcodes can be easily added by including X extensions in the extensions directory and sourcing them by suffixing the -march option with the extension name in the RISC-V accepted usage.

For example:

    rva.tcl -march rv32gc_Xaname

An opcode mnemonic instruction is a Tcl proc that calls 'assemble'. A few pseudo instructions are in macros.tcl and more can easily be added. The macro and alias syntax are slight simplifications of standard Tcl. More complex pseudo instructions benefit by being defined directly as procs.

The currently supported instructions are tested against the gnu gas assembler. The tests are run with make invoking the test scripts.

    make test
    make test-suite   # run the riscv-tests suite if located in an adjacent directory.

A few differences are still present with gas and rva.tcl compressing slightly different sets of instructions and with referencing labels.


All the instructions supported by the assembler are supported here. The disasembler can be used on elf format files and will disassemble all the executable sections with PROGBITS set.

The disassembler is invoked with the -d or -dc switches. The -dc switch allows the display of the compact instruction mnumonics which will otherwise be displayed as 32 bit equlivents.


The emulator can load and run the .lst files produced by the assembler and statically linked elf files files from the risc-v gnu tool chain. The rv32imc and rv64imc instruction sets are fully supported. The only supported system call is 'exit'

The emulator is invoked with -x switch and has an interactive mode enabled with the -v switch.

The emulator is tested by running the riscv-tests generated by the gnu tool chain. The tests can be run by cloning the riscv/riscv-tests repository in an adjacent directory and building it. Then return here and run :

make test-suite All the rv32u[imc] and rv64u[imc] tests should pass. Tests of other instruction set extensions are not invoked.