Use of TCL in Xilinx Vivado 2019

TV It's been a while since I made some significant pages on the good 'ol tcl-er's wiki.

This subject interests me because it's a major application of the script language, and it touches on my long living BWise project, which is a graphical block language, an element of Vivado as well.

The main script language of this Xilinx IDE for their hardware development tools and the now more generally available silicon compilation (from C for instance) tools is Tcl, which means the project management for a chip design for for instance an FPGA as well as the commands for "making" the project steps is Tcl.

I've played with this idea before (I don't remember the page from memory) and for instance included BWise in a long ago Xilinx IDE to play with hardware blocks and make processes graphically. In the latest "Vivado" software (free for the most part for smaller chips) there is in fact a graphical editor for connecting up compute blocks, though I don't know in which language this is programmed (Tk appears to be no part of the installation, only Tcl).

It's easy to find some of the main install dirs, but I though (since Vivado is quite a world wide effort of a big company) maybe someone knows the tcl architecture in these latest packages. It would be fun to play around with a bit, I have a working project comprised of a Zynq processor board with a Silicon compiled C program connected to the A.R.M. processors in the builtin FPGA which compiles nicely in a few minutes on Linux, and it might be interesting to make some fun tcl examples connected.

pdt Also see ttask and specifically the extensions for the Vivado simulator XSim and for the Vivado implementation tools .

Right. Also see an example here: Bwise blocks connecting FPGA accelerated C functions