Version 4 of Clock divider BWise example

Updated 2008-06-06 11:23:18 by LV


First my interests from the page about Network Theoretical Elements in Bwise and second the general interest raised about fundamental computer science (which I cannot help but see in the circuits, not the software) led to this examples of having something (a socket, a proc, a bwise block, an oscillator, a clock pulse) which generates a clock signal, which is a paced, repeated change, which feeds i this case 3 divider blocks to generate derived rates.

The generator in the example could be a high frequerncy generator, which is devided a few hundred times in the dvi1..3 blocks to generate square waves (most likely) which form a minor triad chord at their combined outputs. This happens to be an interesting softwar ematter too, for instance for repeated servicing of times services, especially when they're fine grained.

A simple signal example assuming small binary divider ratio (of course appearing in computer circuits:

 cl:      | 0101010101010101010..
 div1.o:  | 0 1 0 1 0 1 0 1 0 1..
 div2.o:  | 0 0 1 0 0 1 0 0 1 0..
 div3.o:  | 0 0 1 1 0 0 1 1 0 0..

          --> Time

In this signal diagram the div1 block divides by 2, the div2 block divides (necessarily assymetrically) by three, and div3 is a four-divider, meaning their signal repeat in intervals of respectively 2, 3 or 4 input clock cycles. Of cource Proc2 is the clock generator block.

To make the sound of a minor triad musical chord, the blocks would hae to have frequencies which are like the C , Eb and G note, which can be relatively accurately achieved by choosing division factors in the order of a few hundred (9 or more bits dividers in hardware) to get the right frequencies with enough accuracy. In software, this is harder, because the call rate of the main clock procedure would be quite high.

For my example it is interesting to know how the clock is distributed, so where is the cl signal all connected to. In this case there is a standard bwise function to check where the pin cl.out is connected to (In FPGA's this would be interesting problem, too).